# How many hardware (PCI-MSI) interrupts can a PC have?

On my workstation I got only two PCI-MSI interrupts in /proc/interrupts:

  0:   11726919          0    IO-APIC-edge  timer
1:          3          0    IO-APIC-edge  i8042
7:          0          0    IO-APIC-edge  parport0
8:          1          0    IO-APIC-edge  rtc
9:          0          0   IO-APIC-level  acpi
12:          4          0    IO-APIC-edge  i8042
58:         13      94016         PCI-MSI  eth0
169:     843271   71766622   IO-APIC-level  uhci_hcd:usb3, eth1, HDA Intel
201:          1          0   IO-APIC-level  uhci_hcd:usb4, uhci_hcd:usb6
209:          0          0   IO-APIC-level  ehci_hcd:usb1
217:          2          0   IO-APIC-level  ehci_hcd:usb2, uhci_hcd:usb5
225:         27   72309141   IO-APIC-level  uhci_hcd:usb7, eth2
233:       6683     103839         PCI-MSI  ahci
NMI:       2236       4056
LOC:   11696665   11696593
ERR:          0
MIS:          0


On other, much stronger RACK Dell machine (8 cores), there are seven such interrupts.

Does this depend on number of processors? Is IO-APIC-level a software interrupt?

I want to assign PCI-MSI interrupts to my network cards to improve performance.

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IIRC PC can have any number of MSI interrupts. But each device is limited to 32 (for PCI 2.2) or 2048 (for PCI 3.0) MSI interrupts.

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From some basic research it looks like different hardware will have different numbers.

"Each receive DMA channel of a NIC can generate one interrupt, and each interrupt will target one CPU. Sun Multi-threaded 10GbE has 8 receive DMA channels per port, and Quad GbE has 4, so their interrupts can target at most 8 and 4 different CPU, respectively. To avoid interrupt CPU becoming the performance bottleneck, it is recommended to start with a value of the number of receive DMA channels per port or (# of CPU), whichever is lower, so that interrupt loads are distributed to enough CPU."

So we'd need to know your motherboard/proc/NIC to find out what was the best setup.

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"edge" and "level" refer to edge vs level triggering, which is a difference very much in the hardware domain. The distinction only makes sense when talking about the 4 physical interrupt lines of a parallel PCI bus, unless it is a software emulation of such behaviour or on the parallel bus segment behind a PCIe-PCI bridge (which is sometimes used WITHIN extension boards).

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