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I would need an help to solve a problem. I work on a system based on CompactPCI platform. The system is composed by:

  • 3U CompactPCI CPU Blades (based on Pentium M processor)
  • 3U CompactPCI proprietary board equipped with PLX PCI9050 device.

Recently I have changed CPU board with a board based on Intel Core I7.

The problem is that during the PCI configuration phase i cannot read correctly the Base Address Registers for the proprietary board.

These are the results of the PCI scan:

Old (working) configuration (Pentium M CPU board):

  • BAR 0 Mem 128 B. 32 bit. Non-prefetchable.
  • BAR 1 I/O 128 B
  • BAR 2 Mem 2 MB. 32 bit. Non-prefetchable.
  • BAR 3 I/O 64 B

New configuration (Core I7 CPU board):

  • BAR 0 Mem 128 B. 32 bit. Non-prefetchable.
  • BAR 1 I/O 128 B
  • BAR 2 I/O 64 KB
  • BAR 3 Mem 256 MB. 32 bit. Non-prefetchable.

The proprietary board configuration isn't changed.

Can you help me to understand why the pci local memory seen by cpu board is different in the two cases?


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migrated from Aug 31 '11 at 4:27

This question came from our site for professional and enthusiast programmers.

the compact PCI backplane is passive: the PCI bus is driven by the CPU board. obviously, your new CPU board does not enumerate the PCI bus in the same order than the old board, thus BAR 2 and BAR 3 are switched... however, i have no idea how to correct this.

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I expect that base addresses are different but I don't understand why the size of I/O space and memory space are changed. These values are configured in the eprom of proprietary board. – Kevin Aug 30 '11 at 16:48

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