Taken from Qimonda docs:
1) 4GB 2R×4 PC2–5300F–555–11–ZZ
2) 4GB 2R×4 PC2–5300F–555–11–H0
Legend from the data sheet: "The Compliance Code is printed on the module label and describes the speed grade, for example "PC2–6400F–555–11–W0" where 6400F means Fully-Buffered DIMM modules with 6.40 GB/sec Module Bandwidth and "555–11" means Column Address Strobe (CAS) latency =5, Row Column Delay (RCD) latency = 5 and Row Precharge (RP) latency = 5 using the SPD Revision 1.1 and produced on the Raw Card "W"."
Further details in the spec sheets: Both, Raw Card H and Z seem to lead to "# of row/bank/column bits" = "14/3/11"
When 1) works in a system, would 2) ??
