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I think the memories in virtual machines(VMware) are simulative ECC memories, am I right? so I use memspeedc tool test a virtual machines(VMware) and a linux server machine with real ECC memory, comparing with a non-ECC PC memory.

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virtual machine memory test result:

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Reading and writing 32 bits at a time.

Testilg L1 Cache ( 32 KiB):

Sequential read: 1247 MiB/s 3.059 ns

Sequential write: 1642 MiB/s 2.323 ns

Random read: 982 MiB/s 3.883 ns

Random write: 1015 MiB/s 3.760 ns

Interdependant random read: 629 MiB/s 6.065 ns

Testilg L2 Cache (256 KiB):

Sequential read: 1313 MiB/s 2.904 ns

Sequential write: 1649 MiB/s 2.314 ns

Random read: 791 MiB/s 4.821 ns

Random write: 628 MiB/s 6.079 ns

Interdependant random read: 365 MiB/s 10.458 ns

Testing L3 Cache (4 MiB):

Sequential read: 1160 MiB/s 3.289 ns

Sequential write: 1362 MiB/s 2.801 ns

Random read: 109 MiB/s 35.026 ns

Random write: 162 MiB/s 23.493 ns

Interdependant random read: 52 MiB/s 73.360 ns

Testing memory (256 MiB): Sequential read: 1213 MiB/s 3.144 ns Sequential write: 1141 MiB/s 3.344 ns Random read: 61 MiB/s 62.138 ns Random write: 81 MiB/s 47.386 ns Interdependant random read: 27 MiB/s 140.518 ns

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real ECC memory test result:

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Reading and writing 32 bits at a time.

Testilg L1 Cache ( 32 KiB):

Sequential read: 1106 MiB/s 3.450 ns

Sequential write: 1094 MiB/s 3.487 ns

Random read: 829 MiB/s 4.599 ns

Random write: 953 MiB/s 4.005 ns

Interdependant random read: 531 MiB/s 7.181 ns

Testilg L2 Cache (256 KiB):

Sequential read: 1106 MiB/s 3.449 ns

Sequential write: 1086 MiB/s 3.511 ns

Random read: 692 MiB/s 5.511 ns

Random write: 447 MiB/s 8.529 ns

Interdependant random read: 349 MiB/s 10.923 ns

Testing L3 Cache (4 MiB):

Sequential read: 1106 MiB/s 3.449 ns

Sequential write: 1082 MiB/s 3.526 ns

Random read: 442 MiB/s 8.631 ns

Random write: 183 MiB/s 20.836 ns

Interdependant random read: 139 MiB/s 27.384 ns

Testing memory (256 MiB):

Sequential read: 1082 MiB/s 3.527 ns

Sequential write: 966 MiB/s 3.949 ns

Random read: 98 MiB/s 39.041 ns

Random write: 37 MiB/s 103.116 ns

Interdependant random read: 29 MiB/s 130.683 ns

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non-ECC memory test result:

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Reading and writing 32 bits at a time.

Testilg L1 Cache ( 32 KiB):

Sequential read: 6382 MiB/s 0.598 ns

Sequential write: 11907 MiB/s 0.320 ns

Random read: 3071 MiB/s 1.242 ns

Random write: 3336 MiB/s 1.143 ns

Interdependant random read: 1261 MiB/s 3.024 ns

Testilg L2 Cache (256 KiB):

Sequential read: 5897 MiB/s 0.647 ns

Sequential write: 9303 MiB/s 0.410 ns

Random read: 1583 MiB/s 2.409 ns

Random write: 799 MiB/s 4.777 ns

Interdependant random read: 412 MiB/s 9.259 ns

Testing L3 Cache (4 MiB):

Sequential read: 3788 MiB/s 1.007 ns

Sequential write: 1816 MiB/s 2.101 ns

Random read: 302 MiB/s 12.631 ns

Random write: 228 MiB/s 16.727 ns

Interdependant random read: 46 MiB/s 83.384 ns

Testing memory (256 MiB):

Sequential read: 3346 MiB/s 1.140 ns

Sequential write: 1741 MiB/s 2.190 ns

Random read: 79 MiB/s 48.280 ns

Random write: 86 MiB/s 44.242 ns

Interdependant random read: 28 MiB/s 137.046 ns

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Simulating ecc on non-ecc memory would have HUGE overhead and slow everything to a crawl. –  Marc B May 30 '12 at 1:14

1 Answer 1

No, you're wrong, no hypervisor would dream of simulating ECC behaviours to its guests - how would that work anyway?

Anyway, no, that doesn't happen - terribly-worded question by the way.

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