I haven't read that exact passage in the book, but I think I can tell what it's getting at.
Memory is broken up by the processor into "pages." Each page is, on an x86 or x64 processor 4K in size. (Pages can actually be larger in some cases, but let's leave out that complexity right now.) The operating system builds page tables which translate virtual addresses into physical addresses. The processor fetches these page table entries as it executes code so that the software can operate using just virtual addresses.
The virtual addresses are the same as the physical address, for the lower 12 bits of the address, since 4K is 2 to the 12th power.
In an x86 processor with PAE mode turned on, the physical address size is 36 bits. (This was later extended a little bit, and it can be 37 or 38 bits on some machines.) If you subtract the 12 bits that are not specified in the page table entry (because they are the same in the virtual and physical addresses) you are left with 24 bits. Those upper 24 bits of physical address in the page table entry replace the upper bits of the virtual address to make the actual physical address used by the processor.
Note that the virtual address don't have 36 bits. It only has 32 bits. So those upper 24 bits replace the upper 20 bits of virtual address. This points out that, while PAE mode allows the machine to have more than 4GB of memory (4GB is 2 to the 32nd power) no single process can have more than 4GB of virtual memory.