Tag Info

New answers tagged

0

Some pre-Westmere Intel CPU have a somewhat flawed TSC capability, maybe this is your case and the kernel is blacklisting the TSC as a timer source. Issue the following command dmesg | grep -i tsc and report here the output.


0

This page (http://bluecoat.force.com/knowledgebase/articles/Solution/CB-IPdestinationcacheoverflowdstcacheoverflowipdstcachemessage) has instructions for increasing the cache associated with this message - quoted below. However, if you are "under continuous floods" increasing this cache may only make the flooding problem worse, and it is probably better to ...


1

You should run the irqbalance daemon to help distribute interrupts across CPU cores.


3

You can look up the package names along with the distribution name using your favorite search engine for details. My search yielded: https://packages.debian.org/wheezy/linux-image-3.2.0-4-amd64 [...] The Linux kernel 3.2 and modules for use on PCs with AMD64, Intel 64 or VIA Nano processors. This kernel also runs on a Xen hypervisor. It supports both ...



Top 50 recent answers are included