141 reputation
129
bio website ieee-jbdavid.blogspot.com
location San Jose, CA
age 55
visits member for 5 years, 2 months
seen Nov 10 '10 at 9:57
Mixed Signal Design Verification languages: -Verilog (in all its flavors esp Verilog-AMS) -perl -SKILL (the cadence variant of LISP) -(someday) Python & Matlab I manage my own home network and Linux server.. have supported linux user in conjuction with being CAD tool administrator

Jun
21
revised How to ADD one module to initrd using mkinitrd
the answer tested
Jun
21
revised How to ADD one module to initrd using mkinitrd
added 181 characters in body