howto configure memory around the Xeon 56xx CPUs? 2P configuration with 3 channels per CPU
How to fill the DIMM slots for optimum memory performance? what is the minimum number of slots to be filled ?
dual channel, dual rank etc?
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It's not that simple, really, it seems:
Only the high performance parts, X56xx, can reach 6,4 GT/s, 1333 MHz and have to switch down to 5.8 GT/s with a second dimm on a channel. All the other parts (E56xx, L56xx) are maxcapped to 5.8 GT/s, 1066 MHz at best, so they don't switch down with a second dimm anyways. So only X56xx incur bandwidth penalties for a second dimm per channel. (As long as there are no interleaving penalties I'm unaware of.) Have a look at Siliconmechanics info , page 2.
You might want to have a look at Intel® Xeon® Processor 5600 Series Datasheet Volume 2, pages 57 ff and the Intel® Xeon® Processor 5500 Series Datasheet Volume 2 (125 ff) it builds upon. Also You might want to have a look at Siliconmechanics info, which has a nice tables and illustrations on page 2, 5 and 6 or a xeon 5600 applicable server manual , pages 26 ff, at HP.
Oh and You might want to refrain from using 4 rank (quad rank ("qr") dimms instead of 1 (single) rank ("sr") or 2 (double) rank ("dr") dimms.
use single rank if you do lots of contiguous memory IO and 2/4 rank memory if you do lots of random memory IO
Any use of 4 rank dimms seems to limit the cpu to 1066 MHz at best and 800 MHz in most cases. At least the tables 3.2 ff on pages 58 ff of Intel® Xeon® Processor 5600 Series Datasheet Volume 2 say so as far as I understand.
Please have a look or ask a system builder to make sure.