I start a kvm guest(centos6.5) on a Intel machine(centos6.5),use libvirt, the guest's xml as follow

<domain type='kvm' xmlns:qemu='http://libvirt.org/schemas/domain/qemu/1.0'>
  <memory unit='KiB'>8388608</memory>
  <currentMemory unit='KiB'>4194304</currentMemory>
  <vcpu placement='static' current='2'>8</vcpu>
    <type arch='x86_64' machine='rhel6.5.0'>hvm</type>
    <boot dev='hd'/>
    <boot dev='cdrom'/>
    <bootmenu enable='yes'/>
    <bios useserial='yes' rebootTimeout='0'/>
  <cpu mode='host-passthrough'>
  <clock offset='utc'/>
    <disk type='file' device='disk'>
      <driver name='qemu' type='qcow2' cache='none'/>
      <source file='/data/vhosts//test-1.disk'/>
      <target dev='vda' bus='virtio'/>
      <address type='pci' domain='0x0000' bus='0x00' slot='0x05' function='0x0'/>
    <controller type='ide' index='0'>
      <address type='pci' domain='0x0000' bus='0x00' slot='0x01' function='0x1'/>
    <controller type='virtio-serial' index='0'>
      <address type='pci' domain='0x0000' bus='0x00' slot='0x04' function='0x0'/>
    <controller type='usb' index='0'>
      <address type='pci' domain='0x0000' bus='0x00' slot='0x01' function='0x2'/>
    <interface type='bridge'>
      <mac address='52:54:00:ea:12:d9'/>
      <source bridge='br-ex'/>
      <model type='virtio'/>
      <address type='pci' domain='0x0000' bus='0x00' slot='0x03' function='0x0'/>
    <serial type='pty'>
      <target port='0'/>
    <console type='pty'>
      <target type='serial' port='0'/>
    <input type='mouse' bus='ps2'/>
    <graphics type='vnc' port='-1' autoport='yes' listen=''>
      <listen type='address' address=''/>
      <model type='cirrus' vram='9216' heads='1'/>
      <address type='pci' domain='0x0000' bus='0x00' slot='0x02' function='0x0'/>
    <memballoon model='virtio'>
      <address type='pci' domain='0x0000' bus='0x00' slot='0x06' function='0x0'/>
    <qemu:env name='SPICE_DEBUG_ALLOW_MC' value='1'/>

Now I am confused,Despite the use of "host-passthrough",I still can't see L3 cache in guest,only have L1,L2 cache,as follow

[root@vm-kvm-115 results]# lscpu 
Architecture:          x86_64
CPU op-mode(s):        32-bit, 64-bit
Byte Order:            Little Endian
CPU(s):                2
On-line CPU(s) list:   0,1
Thread(s) per core:    1
Core(s) per socket:    1
Socket(s):             2
NUMA node(s):          1
Vendor ID:             GenuineIntel
CPU family:            6
Model:                 26
Stepping:              5
CPU MHz:               2266.746
BogoMIPS:              4533.49
Hypervisor vendor:     KVM
Virtualization type:   full
L1d cache:             32K
L1i cache:             32K
L2 cache:              4096K
NUMA node0 CPU(s):     0,1

Following are my physical machine information

[root@host-kvm-22 linux]# rpm -qa | grep libvirt

[root@host-kvm-22 linux]# rpm -qa | grep qemu

[root@host-kvm-22 linux]# uname -r

[root@host-kvm-22 linux]# lscpu 
Architecture:          x86_64
CPU op-mode(s):        32-bit, 64-bit
Byte Order:            Little Endian
CPU(s):                16
On-line CPU(s) list:   0-15
Thread(s) per core:    2
Core(s) per socket:    4
Socket(s):             2
NUMA node(s):          2
Vendor ID:             GenuineIntel
CPU family:            6
Model:                 26
Stepping:              5
CPU MHz:               2266.743
BogoMIPS:              4532.68
Virtualization:        VT-x
L1d cache:             32K
L1i cache:             32K
L2 cache:              256K
L3 cache:              8192K
NUMA node0 CPU(s):     0-3,8-11
NUMA node1 CPU(s):     4-7,12-15

Can anyone tell me how to enable the L3 cache on guest?

  • 1
    It doesn't matter; the machine is virtual! Nov 20 '15 at 7:28
  • Yes I'm agree with Michael... it's used by a single core and your vps inherits it. Nov 20 '15 at 8:26
  • As you say,my vps inherits it,then it should also inherit L3 cache,Is not it?
    – jython.li
    Nov 20 '15 at 8:56
  • It does matters. Just because it wasn't exposed back then doesn't mean it didn't have a perf impact all that time. Nov 12 '20 at 18:11

FWIW, you're misunderstanding the scope of the host-passthrough CPU model. It only controls identification of the CPU and its feature flags - some aspects of the CPU are still not exposed to the guest. For example with the XML you have there, all 8 CPUs are exposed to the guest as separate sockets in the same NUMA node. Your host instead have 2 NUMA nodes, each with two sockets, each with four cores. That alone is probably enough to make the concept of L3 cache in the host not map well into the guest.

You can setup the virtual CPU topology in the XML, but I still don't think it'd make the L3 cache appear. It also doesn't really matter, because you're allowing 8 virtual CPUs to float across all 16 host CPUs. Since your host CPUs spread across 2 NUMA nodes, you're going to be getting cross-NUMA node memory access much of time which has a high latency penalty, which will wipe out any benefit of the cache. IOW, you'd be far better to focus on more efficient VM placement, by using CPU pinning to confine the guest to a single host NUMA node.


L3 cache support is added to QEMU from version 2.8.0. See Bugzilla.

Exposing L3 cache to guest will improve performance as guest CPUs can avoid a lot of IPI (Inter-Processor Interrupt). Please read this article for more information.

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