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jbdavid
  • Member for 15 years, 1 month
  • Last seen more than 13 years ago
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Mixed Signal Design Verification languages: -Verilog (in all its flavors esp Verilog-AMS) -perl -SKILL (the cadence variant of LISP) -(someday) Python & Matlab I manage my own home network and Linux server.. have supported linux user in conjuction with being CAD tool administrator
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